1. Field of the Invention
The present invention provides an output buffer circuit in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, there has appeared a reduction to 3.3 V of a low power voltage used for driving semiconductor memory devices with a capacity in the range from 4 Mbits to 16 Mbits. Such reduction of the power voltage level renders it difficult to obtain the necessary output voltage of 2.4 V. In the prior art, in order to obtain the necessary output voltage, there is carried out a boost up of a voltage level of the gate of the MOS transistor which performs a switching operation for supplying a high level voltage to the output terminal of the output buffer circuit so that the high level corresponds to the power supply voltage. Conventional boost up circuits for boosting up the output voltage have utilized a capacitor or capacitors which are charged for the boost up only when the logic gate outputs a logic signal as an instruction of the output of the high voltage level from the output terminal of the output buffer circuit. Since the capacitor for the boost up operation begins to charge just before the logic signal is shifted between the high and low levels, there is a considerable necessary time for the charge up of the capacitor for obtaining the boost up of the output voltage which appears on the output terminal, thereby rendering it difficult to allow the output buffer circuit to show a high speed output performance for outputting a sufficiently high output voltage.
A conventional circuit configuration of the output buffer circuit will hereinafter be described with reference to FIG. 1. The conventional output buffer circuit is provided between logic gates and an output terminal 414 and biased by a power supply line which supplies a power supply voltage Vcc and a ground line which supplies a ground voltage. An output stage of the logic circuit comprises first and second NAND gates 401 and 402. An output stage of the output buffer circuit has first and second output n-channel MOS transistors 412 and 415, wherein the first output n-channel MOS transistor 412 is provided in series between the power supply line and the output terminal 414 of the output buffer circuit. The second output n-channel MOS transistor 415 is provided between the ground line and the output terminal 414 of the output buffer circuit. The first output n-channel MOS transistor 412 shows a switching operation associated with digital signals supplied by the first NAND gate 401. The second output n-channel MOS transistor 415 shows a switching operation associated with digital signals supplied by the second NAND gate 402. The first NAND gate 401 has two input terminals, one of which is provided for receipt of a digital signal "OUTH" and another is for receipt of an output enable signal "OE".
The second NAND gate 402 has two input terminals, one of which is provided for receipt of a digital signal "OUTL" and another is for receipt of an output enable signal "OE". The second NAND gate 402 has an output terminal coupled to an input terminal of an inverter 413 which has an output terminal coupled to a gate of the second output n-channel MOS transistor 415. The second output n-channel MOS transistor 415 has a drain coupled to the output terminal 414 of the output buffer circuit and a source coupled to the ground line. Logic signals from the output terminal of the second NAND gate 402 are inverted by the inverter 413 and then inputted into the gate of the second output n-channel MOS transistor 415.
The first NAND gate 401 has an output terminal coupled to gates of p-channel and n-channel MOS transistors 403 and 404 and further coupled to an input terminal of an inverter 405. The p-channel and n-channel MOS transistors 403 and 404 are provided to form the complementary MOS circuit. The p-channel MOS transistor 403 is coupled to the ground line and the n-channel MOS transistor is coupled to the power supply line. An output terminal of the complementary MOS circuit is coupled via an n-channel MOS transistor 407 to the gate of the first output n-channel MOS transistor 412. The output terminal of the first NAND gate 401 is coupled via an inverter 405 to a delay circuit 406. A NAND gate 409 has two input terminals, one of which is coupled to an output terminal of the delay circuit 406 and another input terminal is coupled to the input side of the delay circuit 406. An output terminal of the NAND gate 409 is coupled via an n-channel MOS transistor 408 to a gate of the n-channel MOS transistor 407. A gate of the n-channel MOS transistor 408 is coupled to the power supply line. The output terminal of the NAND gate 409 is coupled to an input terminal of the inverter 410 which has an output terminal coupled via a capacitor 411 to the gate of the first output n-channel MOS transistor 412.
When the NAND gate 401 outputs a high level signal, the p-channel MOS transistor 403 turns OFF and the n-channel MOS transistor 404 turns ON thereby the ground voltage is supplied via the n-channel MOS transistor 404 to the n-channel MOS transistor 407. The low level signal is also supplied to the inverter 405 and inverted by the inverter 405 into the high level signal. The high level signal is supplied to the delay circuit 406 which supplies the high level signal with a time delay. The high level signal with the time delay is then supplied to the input terminal of the NAND gate 409. The high level signal without any time delay is also supplied with the NAND gate 409. For an initial time duration, the NAND gate 409 outputs the high level signal and subsequently outputs the low level signal. For the initial time duration, the high level signal is inputted into the inverter 410 and then inverted into the low level signal which is further applied onto the capacitor 411. However, for the subsequent time duration, the NAND gate 409 outputs the low level signal which is supplied via the n-channel MOS transistor 408 into the gate of the n-channel MOS transistor 407 thereby the n-channel MOS transistor 407 turns OFF. On the other hand, the low level signal is supplied to the inverter 410 and then inverted into the high level signal which is further applied with the capacitor 411. As a result, the capacitor 411 is charged up where the n-channel MOS transistor is in the OFF state. The gate of the first output n-channel MOS transistor 412 is charged up with a considerable time delay and then turns ON thereby the power supply voltage appears with the considerable time delay. This means that the output buffer circuit which utilizes a capacitor for boosting up the high voltage level is engaged with the issue of a response time delay.
Another conventional output buffer circuit is disclosed and illustrated in FIG. 2. This conventional output buffer circuit is provided between the logic gates, for example, first and second NAND gates 501 and 502 and an output terminal 516. First and second output n-channel MOS transistors 515 and 517 are provided between a power supply line and a ground line. The first n-channel MOS transistor 515 is coupled between the power supply line Vcc and the output terminal 516. The second n-channel MOS transistor 517 is coupled between the ground line and the output terminal 516. The gate of the second output n-channel MOS transistor 517 is coupled via an inverter 514 to the second NAND gate 502. The gate of the first output n-channel MOS transistor 515 is coupled via a complementary MOS circuit to the first NAND gate 501 wherein the complementary MOS circuit comprises p-channel and n-channel MOS transistors 512 and 513. The n-channel MOS transistor 513 is coupled to the ground line and the p-channel MOS transistor 512 is coupled via an n-channel MOS transistor 508 to the power supply line. The n-channel MOS transistor 512 is also coupled via a capacitor 511 to an output side of a complementary MOS circuit comprising p-channel and n-channel MOS transistors 509 and 510. An input terminal of the complementary MOS circuit is coupled to the output terminal of the first NAND gate 501 and coupled via a capacitor 505 and n-channel MOS transistors 503 and 504 to the power supply line Vcc. The n-channel MOS transistors have diode connections wherein gates thereof are coupled to drain sides thereof respectively. The drain of the n-channel MOS transistor 504 is coupled to a gate of the n-channel MOS transistor 508. An n-channel MOS transistor 507 is coupled between the power supply line and the gate of the n-channel MOS transistor 508. A gate of the n-channel MOS transistor 507 is coupled to the drain of the n-channel MOS transistor 508. An n-channel MOS transistor 506 is coupled between the power supply line and the gate of the n-channel MOS transistor 508. A gate of the n-channel MOS transistor 506 is coupled to the power supply line Vcc.
The above two conventional output buffer circuits have the following disadvantages. The boosting up operation of the gate of the output MOS transistor is commenced after the charge up operation of the gate thereof up to the power supply voltage. The boosting up operation is thus completed with a large time delay. If the timing of the commencement of the boosting up operation is set earlier than the necessary time, this results in an insufficient voltage level boosted up thereby the output n-channel MOS transistor provides a certain voltage drop from the power supply voltage. Therefore, the above two conventional output buffer circuits are unable to satisfy both the requirements for the high speed response and the sufficiently high driving voltage level applied to the gate of the output MOS transistor coupled between the power supply line and the output terminal of the output buffer circuit. For that reason, it had been required to develop a quite novel output buffer circuits which is capable of satisfying the above both requirements for the high speed response and the sufficiently high driving voltage level applied to the gate of the output MOS transistor coupled between the power supply line and the output terminal of the output buffer circuit.